1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor memory having a bitline precharge circuit.
2. Background of the Related Art
FIG. 1 shows portions of a related art DRAM memory cell array, a bitline precharge circuit connected to the array and sense amplifiers. Each of the bitlines BL0,/BLO, BL1 and/BL1 consist of two parts `B1` and `B2` that are connected by NMOS transistors Q1 to Q4, which are bitline isolation switching devices. The `B1` and `B2` parts are connected electrically only when the NMOS transistors Q1 to Q4 are enabled (i.e., an ON-state).
The `B1` is a portion of the bitline connected to the memory cell array MC1 to MC4, etc. When a bitline precharge voltage VBLP of VDD/2 is applied to bitline precharge circuit BLP0 and BLP1 and a bitline equalizing signal /BEQi is activated to low level, the `B1` part is precharged by the voltage of VDD/2.
The `B2` of the bitlines includes sense amplifiers S/A0 and S/A1. After being amplified in the sense amplifiers S/A0 and S/A1 to the voltage level of VDD and VSS respectively, the data having been loaded in the `B1` is supplied to the `B2`. NMOS transistors Q5 to Q8 are switching devices between the `B2` of the bitline and the data bus. The data having been loaded in the `B2` is loaded in the data bus DB and /DB as soon as the NMOS transistors Q5 to Q8 are enabled (i.e., an ON-state).
As described above, the reason the `B1` of the bitline connected to the memory cell array is precharged to the level of VDD/2 is that the time required for reading each data of `1` and `0` is well balanced. If the bitlines BL and /BL were precharged to the level of VDD, the time required for reading the data of `0` is much longer than the time required for reading the data of `1`. Such asymmetry prevents optimizing the DRAM operation. However, the time required for reading the data of `1` is the same as `0` while the bitlines BL and /BL are precharged with the voltage of VDD/2, which optimizes the DRAM operation.
Accordingly, an actual voltage level of the data loaded from the memory cell to the bitlines is not high because the capacitance of the storage capacitor of the memory cell is very small to increase integration, increase capacity and to provide a high DRAM operating speed. Even though the data is loaded in the bitline has been precharged, the voltage level has little variation. Having detected the slight variation, the sense amplifier amplifies the slight voltage level variation. Consequently, the accurate precharge and the equalization of the bitlines has a great significance in DRAM.
FIG. 2 shows the circuit of the blocks denoted by 100 and 200 in detail. Referring to FIG. 2, two NMOS transistors Q10 and Q11 are connected in series between the bitlines BL0 and /BL0, and the other NMOS transistor Q12 is connected in parallel to the two NMOS transistors Q10 and Q11 between the bitlines BL0 and /BL0. The bitline precharge voltage is supplied to a node at which the drains of the NMOS transistors Q10 and Q11 are reciprocally connected. The gates of the NMOS transistors Q10 to Q12 are regulated by the bitline equalizing signal /BEQi. The bitline equalizing signal /BEQi decided by a DRAM /RAS signal becomes low level as soon as the /RAS signal becomes low level, whereby the precharge and the equalizing operation are not performed. When the /RAS signal becomes high level and the bitline equalizing signal /BEQi becomes high level, the bitlines are precharged and also equalized.
In particular, the bitline precharge voltage VBLP is supplied to the bitlines BL0 and /BL0 by the NMOS transistors Q10 and Q11 of the block 100, which have become on-state according to the high level bitline equalizing signal /BEQi. Simultaneously, the voltage levels of the bitlines BL0 and /BL0 are equalized by electrically shorting the bitlines BL0 and /BLO when the NMOS transistor Q12 becomes enabled according to the bitline equalizing signal /BEQi. In the circuit of the block 200 in FIG. 2, the same precharge and the same equalizing operation are also carried out by the bitline equalizing signal /BEQi.
Further, there are parasitic capacitance and resistance existing in the two bitline precharge circuits, i.e. the blocks 100 and 200 respectively shown in FIG. 2. The parasitic capacitance existing in the bitline precharge circuit, the NMOS transistors Q1 and Q2, the signal lines and the power lines will now be described. The parasitic capacitances Ca1 to Ca6 appear between each of the electrodes such as gates, sources and drains of the NMOS transistors Q10 to Q12. Additional parasitic capacitances C10-C11 and C13-C14 exist within the area defined by the lines of the bitlines BL0 and /BL0, the bitline precharge voltage supplying line 4, and the bitline isolation signal line 6.
Parasitic resistances R10 to R16 appear in the electrodes of each NMOS transistors such as gates, sources and drains, the area surrounded by the lines of the bitlines BL0 and /BLO, the bitline precharge voltage supplying line 4 and the bitline isolation signal line 6. Additional parasitic resistances R17 and R18 also exist between the bitline equalizing signal 5 and the gates of the NMOS transistors Q10 and Q11. The bitline precharge circuit of the block 200 has the same parasitic capacitances and resistances as the block 100.
Normal operation of the circuit will not occur in the DRAM bitline precharge circuit if the parasitic capacitance or the parasitic resistance has different values. The parasitic capacitance and resistance in a semiconductor integrated circuit cannot be excluded completely. Pairs of capacitances such as the capacitances Ca1 and Ca4 and the capacitances Ca2 and Ca3 exist if the origin of the parasitic capacitance is taken as a reference point. The bitlines BL0, /BL0, BL1 and /BL1 are unable to be precharged evenly to the voltage level of VDD/2 unless the values of two parasitic capacitances are identical to each other.
As described above, the related art bitline precharge circuit has various problems. Asymmetry of parasitic capacitance or resistance is primarily caused by the layout pattern in the actual circuit formed on the wafer. Thus, values of corresponding parasitic resistances or capacitances supposed to be symmetric are not identical to each other unless the layout of the circuit is designed symmetrically. Further, asymmetry of the layout pattern causes inefficiency of a circuit layout because of the undesirably enlarged layout area and prevents very high integration.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.